| PART |
Description |
Maker |
| M5LV-512/256-10SAI M5LV-512/256-12SAC M5LV-256/160 |
EE PLD, 10 ns, PBGA352 BGA-352
EE PLD, 12 ns, PBGA352 BGA-352
Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP208
Fifth Generation MACH Architecture EE PLD, 12 ns, PQFP208
Fifth Generation MACH Architecture EE PLD, 20 ns, PQFP160
Fifth Generation MACH Architecture EE PLD, 5.5 ns, PQFP100
Fifth Generation MACH Architecture EE PLD, 15 ns, PQFP160
Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP160
EE PLD, 15 ns, PBGA352 BGA-352
Fifth Generation MACH Architecture EE PLD, 5.5 ns, PQFP144
EE PLD, 15 ns, PQFP160 PLASTIC, QFP-160
CONNECTOR ACCESSORY EE PLD, 5.5 ns, PQFP100
Fifth Generation MACH Architecture EE PLD, 15 ns, PQFP208
Fifth Generation MACH Architecture EE PLD, 7.5 ns, PQFP208
Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP100
EE PLD, 15 ns, PQFP100 TQFP-100
Fifth Generation MACH Architecture EE PLD, 20 ns, PQFP208
EE PLD, 12 ns, PQFP100 TQFP-100
EE PLD, 12 ns, PBGA256 BGA-256
|
Lattice Semiconductor, Corp.
LATTICE SEMICONDUCTOR CORP
|
| CY7C1303AV25-100BZC CY7C1306AV25-100BZC CY7C1303AV |
Memory : Sync SRAMs
18-Mb Burst of 2 Pipelined SRAM with QDR(TM) Architecture
18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Architecture
18-Mb Burst of 2 Pipelined SRAM with QDR Architecture
18-Mb Burst of 2 Pipelined SRAM with QDR?/a> Architecture
|
Cypress Semiconductor
|
| CY7C1561KV18 CY7C1561KV18-400BZC CY7C1561KV18-400B |
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 QDR SRAM, 0.29 ns, PBGA165
72-Mbit QDR-II SRAM 4-Word Burst Architecture
|
Cypress Semiconductor, Corp.
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| CY7C1350 7C1350 |
128Kx36 Pipelined SRAM with NoBL Architecture(带NoBL结构28Kx36流水线式 SRAM) 128K × 36至流水线与总线延迟静态存储器体系结构（带总线延迟结构28K × 36至流水线式的SRAM
128Kx36 Pipelined SRAM with NoBL Architecture(B>NoBL结构28Kx36流水线式 SRAM)
From old datasheet system
|
Cypress Semiconductor Corp.
|
| CY7C1355B-117BGI CY7C1355B-117BZC CY7C1355B-117BGC |
9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture 9 - MB的（256 × 36/512K × 18）流体系结构，通过与总线延迟静态存储器
9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture 256K X 36 ZBT SRAM, 7.5 ns, PBGA165
9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture 256K X 36 ZBT SRAM, 6.5 ns, PBGA165
9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture 256K X 36 ZBT SRAM, 7 ns, PQFP100
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| 89177-6030 89177-6011 |
Edge Connector,PCB Mnt,RECEPT,120 Contacts,0.05 Pitch,PC TAIL Terminal 120 CONTACT(S), FEMALE, STRAIGHT SINGLE PART CARD EDGE CONN, SOLDER
ASSY 1.27 EDGE CONN CARD 120 CONTACT(S), FEMALE, STRAIGHT SINGLE PART CARD EDGE CONN, SOLDER
|
Molex, Inc.
|
| 09-01-1128 |
KK 156 Cmp Hsg Edge Card Rib 12ckt 12 CONTACT(S), FEMALE, SINGLE PART CARD EDGE CONN, CRIMP
|
Molex, Inc.
|
| CY7C1315AV18-250BZC CY7C1311AV18 CY7C1311AV18-167B |
18-Mb QDR(TM)-II SRAM 4-Word Burst Architecture
18-Mb QDRTM-II SRAM 4-Word Burst Architecture
|
CYPRESS[Cypress Semiconductor]
|
| CY7C1305BV25 CY7C1305BV25-100BZC CY7C1305BV25-167B |
18-Mbit Burst of 4 Pipelined SRAM with QD(TM) Architecture
18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
From old datasheet system
|
CYPRESS[Cypress Semiconductor]
|
| 74F109 I74F109D I74F109N N74F109D N74F109N 74F109_ |
Positive J-K positive edge-triggered flip-flops F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
From old datasheet system
Positive J-Knot positive edge-triggered flip-flops
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
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